1. Field of the Invention
The present invention generally relates to the field of semiconductor manufacture, and particularly to a method for forming a metal gate and a method for forming a MOS transistor.
2. Description of Prior Art
In the wake of an ever increasing integration level of semiconductor devices, in a mainstream method for fabricating MOS transistor for advanced semiconductor device, a gate dielectric layer includes high k material with dielectric constant of no less than 10, and a metal gate includes metal material. When a metal gate is formed on a high k gate dielectric layer, a step of polishing interlayer dielectric layer (ILD) is needed before removing a polysilicon gate, which is used as a dummy gate. This step may impact performance of the metal gate formed in a subsequent step. Thus, chemical mechanical polishing (CMP) of ILD is critical. A conventional method for forming a metal gate is disclosed in, for example US Pat. publication No. 20100109088, and comprises: defining an active region with shallow trench isolations on a substrate, defining a pFET active region with a hard mask, and etching the pFET active region. At a region exempt from etching, a SiGe layer grows to be substantially flush with the substrate. The hard mask is removed to form a gate material layer on the substrate. The gate material layer is patterned to form a metal gate stack. Ions are implanted into the active region to form metal gate stack spacers. A source and a drain are respectively formed on the substrate.
FIGS. 1-6 exemplarily show a conventional method for forming a metal gate.
As shown in FIG. 1, a sacrificial oxide layer 2 and a polysilicon gate 3 are respectively formed on the substrate 1 in sequence. A silicon oxide layer 4 is formed on the substrate 1 and on sidewalls of the sacrificial oxide layer 2 and the polysilicon gate 3. A stop layer 5 is formed on the substrate 1 and covers the silicon oxide layer 4 and the polysilicon gate 3. An interlayer dielectric layer 6 is formed on the stop layer 5.
As shown in FIG. 2, the interlayer dielectric layer 6 is polished by a CMP process for exposing the stop layer 5 on the polysilicon gate 3.
As shown in FIG. 3, the interlayer dielectric layer 6 and the stop layer 5 are polished by CMP process for exposing the polysilicon gate 3. In one embodiment, slurry is chosen in such a way that removal rate of the interlayer dielectric layer 6 is larger than removal rate of the stop layer 5. When the polysilicon gate 3 is exposed, the stop layer 5 is substantially flush with the polysilicon gate 3, and the interlayer dielectric layer 6 is lower than the stop layer 5.
As shown in FIG. 4, the polysilicon gate 3 is removed to expose the sacrificial oxide layer 2. The sacrificial oxide layer 2 is removed for exposing the substrate 1 and forming a trench (not labeled). A metal layer is formed on the interlayer dielectric layer 6, and is filled into the trench. The metal layer is polished for forming the metal gate 8 in the trench. Referring to FIG. 4, the interlayer dielectric layer 6 is lower than the stop layer 5. Metal residuals are remained on the interlayer dielectric layer 6 after formation of the metal gate 8. Shortcut may occur, resulting in deterioration of performance.
As shown in FIG. 5, slurry is chosen so that removal rate on the stop layer 5 is larger than that on the interlayer dielectric layer 6. Especially in a device-intensive region, when the interlayer dielectric layer 6 is polished to such a height that the stop layer 5, the silicon oxide layer 4 and the polysilicon gate 3 are all lower than the interlayer dielectric layer 6, undesired recesses 7 may be formed.
As shown in FIG. 6, during formation of the metal gate 8, the recesses 7 are filled with metal, resulting in metal bridge and metal residuals. Shortcut may occur, tending to cause deterioration of electrical performance.